一种高性能极化码Fast-SSC译码器设计

林青; 杜高明; 戴吴骏; 王晓蕾

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一种高性能极化码Fast-SSC译码器设计

更新时间：2026-09-04

- 一种高性能极化码Fast-SSC译码器设计
- Design of a high-performance fast-SSC decoder for polar codes
- 微电子学与计算机 2021年38卷第2期页码：7-13
- 作者机构：
  
  合肥工业大学微电子设计研究所教育部IC网上合作研究中心,安徽,合肥,230601
- 作者简介：
- 基金信息：
  
  国家重点研发计划 2018YFB2202604安徽高校协同创新项目 GXXT-2019-030
- DOI：
  中图分类号：
- 纸质出版：2021
- 稿件说明：
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林青, 杜高明, 戴吴骏, 王晓蕾. 一种高性能极化码Fast-SSC译码器设计[J]. 微电子学与计算机, 2021, 38(2): 7-13, 18.

LIN Qing, DU Gao-ming, DAI Wu-jun, et al. Design of a high-performance fast-SSC decoder for polar codes[J]. 2021, 38(2): 7-13.
林青, 杜高明, 戴吴骏, 王晓蕾. 一种高性能极化码Fast-SSC译码器设计[J]. 微电子学与计算机, 2021, 38(2): 7-13, 18. DOI：

LIN Qing, DU Gao-ming, DAI Wu-jun, et al. Design of a high-performance fast-SSC decoder for polar codes[J]. 2021, 38(2): 7-13. DOI：

摘要

为了进一步降低无线通信系统中信道编码极化码Fast-SSC译码器的译码延迟和硬件资源消耗，本文提出了两种对Fast-SSC译码算法的优化方法，基于FPGA硬件实现了码长=1 024优化的Fast-SSC译码器.基于Fast-SSC译码树上的四种特殊结点Rate0、Rate1、Rep和SPC，提出分别以Rate0结点和Rep结点为基础进行组合型特殊结点的拓展，使译码树上的特殊结点类型由原来的四种增加至十种以上，进一步加快了搜索译码树的速度；提出存储器资源复用的方法，相同译码树深度的结点使用相同的存储空间.综合结果表明最大工作频率为169 MHz，译码延迟为1.71 μs，数据吞吐率为599 Mbps，存储器消耗为14.8 Kbit，有效提升了Fast-SSC译码器的整体性能.

Abstract

In order to further reduce the decoding delay and hardware resource consumption of the Fast-SSC decoder of channel-coded polarized code in wireless communication system

this paper proposes two optimization methods for the Fast-SSC decoding algorithms

and realizes the fast-SSC decoder optimized with code length =1 024 based on FPGA hardware. Based on the four special nodes Rate0

Rate1

Rep

and SPC in the fast-SSC decoding tree

the expansion of combined special nodes based on the Rate0 node and the Rep node respectively is proposed

which makes the special nodes in the decoder tree increase from the original four to more than ten

further speeding up the speed of searching decoder tree. A method of multiplexing memory resources is proposed in which nodes with the same decoding tree depth use the same storage space. The comprehensive results show that the maximum operating frequency is 169 MHz

the decoding delay is 1.71 μs

the data throughput is 599 Mbps

and the memory consumes 14.8 Kbit

which effectively improves the overall performance of the Fast-SSC decoder.

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Keywords

references

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