同步寄存器链中误码率的亚稳态分析

王郑毅; 刘文波; 代少飞; 李开宇; 朱鹏飞

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同步寄存器链中误码率的亚稳态分析

更新时间：2026-09-04

- 同步寄存器链中误码率的亚稳态分析
- Metastability analysis of error rate in synchronization chains
- 微电子学与计算机 2021年38卷第5期页码：14-18
- 作者机构：
  
  1. 南京航空航天大学自动化学院,江苏,南京,210000
  2. 高速载运设施的无损检测监控技术工信部重点实验室,江苏,南京,211006
- 作者简介：
- 基金信息：
  
  国家重点研发计划 2018YFB2003304国家自然科学基金 61871218
- DOI：
  中图分类号：
- 纸质出版：2021
- 稿件说明：
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王郑毅, 刘文波, 代少飞, 李开宇, 朱鹏飞. 同步寄存器链中误码率的亚稳态分析[J]. 微电子学与计算机, 2021, 38(5): 14-18.

WANG Zheng-yi, LIU Wen-bo, DAI Shao-fei, et al. Metastability analysis of error rate in synchronization chains[J]. 2021, 38(5): 14-18.
王郑毅, 刘文波, 代少飞, 李开宇, 朱鹏飞. 同步寄存器链中误码率的亚稳态分析[J]. 微电子学与计算机, 2021, 38(5): 14-18. DOI：

WANG Zheng-yi, LIU Wen-bo, DAI Shao-fei, et al. Metastability analysis of error rate in synchronization chains[J]. 2021, 38(5): 14-18. DOI：

摘要

数字电路的亚稳态现象会导致数据发生误码，同步寄存器链常常被用于降低亚稳态发生的概率.为了量化由亚稳态导致的数据误码发生概率，本文从亚稳态产生的本质出发分析了亚稳态在同步寄存器链中传递的原因；推导了考虑线延迟与逻辑门延迟影响的精确亚稳态稳定时间公式；设计了一种新亚稳态测试电路计算三种亚稳态输出结果发生的概率.在平均故障时间参数的基础上，计算了因为亚稳态而造成的同步寄存器链误码率和整个系统的误码率，给出了降低系统误码率的措施.

Abstract

Metastability of digital circuits can lead to data error. Synchronous register chains are often used to reduce the probability of metastability. In order to quantify the probability of data error caused by metastable state

this paper analyzes the reason of metastable transfer in synchronous register chain according to the essence of metastable state. The precise formula of metastable stability time considering the effect of linear delay and logic gate delay is derived. A new metastable test circuit is designed to calculate the probability of occurrence of three metastable output results. Based on the mean time to failure (MTBF)

the bit error rate (BER) of synchronization chain and the whole system due to metastability are calculated

and the measures to reduce the BER of the system are given.

关键词

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references

黄忠朝, 赵于前. 一种实现高速异步FIFO的FPGA方法[J]. 计算机工程与应用, 2010, 46(3): 13-15. DOI: 10.3778/j.issn.1002-8331.2010.03.004. HUANG Z C, ZHAO Y Q. Implementation method of high-speed asynchronous FIFO using FPGA[J]. Computer Engineering and Applications, 2010, 46(3): 13-15. DOI: 10.3778/j.issn.1002-8331.2010.03.004.

俞帆, 张伟欣. FPGA设计中的跨时钟域问题[J]. 现代电子技术, 2014, 37(7): 151-153. DOI: 10.3969/j.issn.1004-373X.2014.07.044. YU F, ZHANG W X. Problem of clock domain crossing in FPGA design[J]. Modern Electronics Technique, 2014, 37(7): 151-153. DOI: 10.3969/j.issn.1004-373X.2014.07.044.

金大超, 冷建伟. 异步时钟域信号同步的实现[J]. 天津理工大学学报, 2017, 33(3): 40-44. DOI: 10.3969/j.issn.1673-095X.2017.003.009. JIN D C, LENG J W. Implementation of asynchronous clock domain signal synchronization[J]. Journal of Tianjin University of Technology, 2017, 33(3): 40-44. DOI: 10.3969/j.issn.1673-095X.2017.003.009.

蒲石. 异步多时钟域系统的同步设计研究[D]. 西安: 西安电子科技大学, 2007. PU S. The study of synchronizer design in asynchronous clock domain system[D]. Xi'an: Xidian University, 2007.

徐翼, 郑建宏. 异步时钟域的亚稳态问题和同步器[J]. 微计算机信息, 2008, 24(5): 271-272. DOI: 10.3969/j.issn.1008-0570.2008.05.111. XU Y, ZHENG J H. Metastability in the asynchronous clocks and Synchronizer[J]. Microcomputer information, 2008, 24(5): 271-272. DOI: 10.3969/j.issn.1008-0570.2008.05.111.

于海, 樊晓桠. 基于FPGA异步FIFO的研究与实现[J]. 微电子学与计算机, 2007, 24(3): 210-213. DOI: 10.3969/j.issn.1000-7180.2007.03.059. YU H, FAN X Y. Research and implementation of asynchronous FIFO based on FPGA[J]. Microelectronics % Computer, 2007, 24(3): 210-213. DOI: 10.3969/j.issn.1000-7180.2007.03.059.

Altera Corporation. Metastability in Altera devices[R]. UK: Altera Corporation, 1998.

黄凡. 一种基于FPGA的异步FIFO设计方法[J]. 微处理机, 2017, 38(1): 23-26. DOI: 10.3969/j.issn.1002-2279.2017.01.007. HUANG F. Design of asynchronous FIFO based on FPGA[J]. Microprocessors, 2017, 38(1): 23-26. DOI: 10.3969/j.issn.1002-2279.2017.01.007.

汪路元. FPGA设计中的亚稳态及其缓解措施[J]. 电子技术应用, 2012, 38(8): 13-15. DOI: 10.3969/j.issn.0258-7998.2012.08.004. WANG L Y. Metastable state and mitigation measures in FPGA design[J]. Application of Electronic Technique, 2012, 38(8): 13-15. DOI: 10.3969/j.issn.0258-7998.2012.08.004.

New York ARORA M. The art of hardware architecture: design methods and techniques for digital circuits[M]. New York: Springer, 20 1 1: 1- 10. DOI: 10. 1007/978- 1-46 14-0397-5.

田毅, 范毓洋, 李哲玮, 等. 基于FPGA的亚稳态参数测量方法[J]. 微电子学与计算机, 2016, 33(10): 46-49. DOI: 10.19304/j.cnki.issn1000-7180.2016.10.010. TIAN Y, FAN Y Y, LI Z W, et al. Metastable parameter measurement method based on FPGA[J]. Microelectronics % Computer, 2016, 33(10): 46-49. DOI: 10.19304/j.cnki.issn1000-7180.2016.10.010.

肖军. 探讨FPGA设计中的关键问题[J]. 通信电源技术, 2017, 34(1): 80-81. DOI: 10.19399/j.cnki.tpt.2017.01.030. XIAO J. Discussion on the key problems in FPGA design[J]. Telecom Power Technology, 2017, 34(1): 80-81. DOI: 10.19399/j.cnki.tpt.2017.01.030.

姜群兴, 朱怀宇. FPGA亚稳态处理方法研究[J]. 工业控制计算机, 2020, 33(2): 33-35. DOI: 33 JIANG Q X, ZHU H Y. Research on FPGA metastable processing method[J]. Industrial Control Computer, 2020, 33(2): 33-35. DOI: 33

黄隶凡, 郑学仁. FPGA设计中的亚稳态研究[J]. 微电子学, 2011, 41(2): 265-268. DOI: 265 HUANG L F, ZHENG X R. Study on metastability in FPGA design[J]. Microelectronics, 2011, 41(2): 265-268. DOI: 265

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