一种多信号可配置的低功耗AFE电路设计

涂家华; 殷树娟

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一种多信号可配置的低功耗AFE电路设计

更新时间：2026-09-04

- 一种多信号可配置的低功耗AFE电路设计
- Design of a multi-signal configurable low-power AFE circuit
- 微电子学与计算机 2021年38卷第3期页码：46-50
- 作者机构：
  
  北京信息科技大学机构理学院,北京,100192
- 作者简介：
- 基金信息：
  
  国家自然科学基金 61604014北京市教委科技面上项目 71E1810981
- DOI：
  中图分类号：
- 纸质出版：2021
- 稿件说明：
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涂家华, 殷树娟. 一种多信号可配置的低功耗AFE电路设计[J]. 微电子学与计算机, 2021, 38(3): 46-50.

TU Jia-hua, YIN Shu-juan. Design of a multi-signal configurable low-power AFE circuit[J]. 2021, 38(3): 46-50.
涂家华, 殷树娟. 一种多信号可配置的低功耗AFE电路设计[J]. 微电子学与计算机, 2021, 38(3): 46-50. DOI：

TU Jia-hua, YIN Shu-juan. Design of a multi-signal configurable low-power AFE circuit[J]. 2021, 38(3): 46-50. DOI：

摘要

为提高可穿戴式医疗芯片的集成度、降低芯片整体功耗和工艺成本，提出了一种多信号可配置的低功耗模拟前端电路.该电路其主要采用了C类反相器和全互补耗尽区MOS电容技术，设计了集成了带有可配置高通滤波功能的仪表放大器、低功耗可配置增益放大器和带宽可配置的低功耗低通滤波器等模块.该模拟前端电路采用SMIC 0.18 m CMOS工艺设计，仿真结果表明：功耗为52.8 W，CMRR为76.1 dB，输入参考噪声功率谱密度为3.45 V/sqrt(Hz).

Abstract

In order to improve the integration of wearable medical chips and reduce thewholepowerconsumption and the process cost

a multi-signal configurable low-power AFE circuit in standard digital technology is proposed

which mainlyadopts Class-C inverters and full compensated depletion-mode MOS-capacitorsto constitutean instrumentation amplifier with configurable high-pass filtering frequency

a low-power configurable gain amplifier and a low-power LPF with configurable bandwidth. In this circuit

Class C inverters and fully complementary depletion region MOS capacitor technology are adopted

and instrument amplifier with configurable high-pass filter function

low-power configurable gain amplifier and low-power low-pass filter with bandwidth configurable module are designed and integrated. The proposed AFE circuit is implemented in SMIC 0.18 m CMOS process.Simulation results show that the power consumption is 52.8 W

the CMRR is 76.1 dB

and the input-reference-noise PSD is 3.45 V / sqrt (Hz).

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references

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