基于Chisel语言的RISC-V处理器设计技术

娄冕; 张海金; 杨靓; 刘思源; 赵亮

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基于Chisel语言的RISC-V处理器设计技术

更新时间：2026-09-04

- 基于Chisel语言的RISC-V处理器设计技术
- Design of RISC-V processor based on Chisel
- 微电子学与计算机 2021年38卷第3期页码：51-55
- 作者机构：
  
  西安微电子技术研究所,陕西,西安,710054
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- 纸质出版：2021
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娄冕, 张海金, 杨靓, 刘思源, 赵亮. 基于Chisel语言的RISC-V处理器设计技术[J]. 微电子学与计算机, 2021, 38(3): 51-55.

LOU Mian, ZHANG Hai-jin, YANG Liang, et al. Design of RISC-V processor based on Chisel[J]. 2021, 38(3): 51-55.
娄冕, 张海金, 杨靓, 刘思源, 赵亮. 基于Chisel语言的RISC-V处理器设计技术[J]. 微电子学与计算机, 2021, 38(3): 51-55. DOI：

LOU Mian, ZHANG Hai-jin, YANG Liang, et al. Design of RISC-V processor based on Chisel[J]. 2021, 38(3): 51-55. DOI：

摘要

近年来，RISC-V在处理器领域的大行其道，不仅仅在于其开源可扩展的指令集架构属性，同时也得益于加州大学伯克利分校为其量身打造的敏捷化设计语言Chisel，极大降低了处理器设计门槛.本文基于Chisel语言设计实现了一款带有扩展指令协处理器的多核RISC-V芯片，相对于传统的硬件设计语言，将硬件IP的设计与集成周期压缩50%以上，并且依靠丰富的模板资源，能够快速完成拓扑互连、时序分割、跨时钟域转换等影响处理器整体性能的全局性优化设计，将芯片验证与实现的迭代周期缩短30%以上，为开源处理器敏捷化开发探索了行之有效的技术手段.

Abstract

In recently years

RISC-V′s popularity in the field of processors is not only due to its open-source and extensible instruction set architecture attributes

but also thanks to Chisel

an agile design language tailored by UC Berkeley

greatly reducing the threshold of processor design.A multi-core RISC-V chip with extended instruction coprocessor based on Chiselis designed and implemented in this paper. Compared with the traditional hardware design language

the design and integration time of hardware IP is compressed by more than 50%. At the same time

relying on rich template resources

it can quickly complete the global optimization design that affects the overall performance of the processor

such as topology interconnection

timing segmentation

and cross-clock domain conversion

reducing the iteration time of chip verification and implementation by more than 30%. The open-source processor agile development has explored effective technical means.

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references

LEE Y, WATERMAN A, COOK H, et al. An agile approach to building RISC-V microprocessors[J]. IEEE Micro, 2016, 36(2): 8-20. DOI: 10.1109/MM.2016.11.

MAHAPATRA A, SCHAFER B C. VeriIntel2C: abstracting RTL to C to maximize high-level synthesis design space exploration[J]. Integration, 20 19(64): 1- 12. DOI: 10. 10 16/j.vlsi.20 18.03.0 1 1.

BACHRACH J, VO H, RICHARDS B, et al. Chisel: constructing hardware in a scalaembedded language[C]//DAC Design Automation Conference 2012. San Francisco: IEEE, 2012. DOI: 10.1145/2228360.2228584.

NAN L M, YANG X, ZENG X Y, et al. A VLIW architecture stream cryptographic processor for information security[J]. China Communications, 2019, 16(6): 185-199. DOI: 10.23919/JCC.2019.06.015.

BAE G, BAE DI, KANG M, et al. 3nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications[C]//Proceedings of 2018 IEEE International Electron Devices Meeting.San Francisco: IEEE, 2018. DOI: 10.1109/IEDM.2018.8614629.

余子濠, 刘志刚, 李一苇, 等. 芯片敏捷开发实践: 标签化RISC-V[J]. 计算机研究与发展, 2019, 56(1): 35-48. DOI: 35 YU Z H, LIU Z G, LI Y W, et al. Practice of chip agile development: labeled RISC-V[J]. Journal of Computer Research and Development, 2019, 56(1): 35-48. DOI: 35

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