1. 中国科学院微电子研究所 机构,北京,121002
2. 中国科学院大学 机构,北京,101408
3. 杭州中科微电子有限公司,浙江,杭州,310053
纸质出版:2021
移动端阅览
张洁, 何文涛, 冯华星. 基于直流无刷电机的PWM电路设计[J]. 微电子学与计算机, 2021, 38(3): 84-88.
ZHANG Jie, HE Wen-tao, FENG Hua-xing. The design of PWM circuit based on DC brushless motor[J]. 2021, 38(3): 84-88.
针对直流无刷电机驱动系统存在的模拟PWM技术控制难、PWM芯片少以及PWM死区时间精度低等问题,本文采用Verilog语言设计了一款纯数字电路实现的PWM波形生成器.文中简要介绍了PWM在直流无刷电机系统的控制原理、电机转子位置和电机相导通的关系及PWM调制方式,重点描述了采用纯数字方法实现PWM波形发生器的设计流程.通过增加时钟除频模块,死区计数时钟频率可提高到PWM计数器的16倍;两通道PWM共用一个死区计数器,节省了设计资源.设计的PWM波形生成器可通过SPI接口进行参数配置,实现可编程、方便控制等优点.
In view of the problems in the brushless DC motor drive system
such as the difficulty of analog PWM technology control
the lack of PWM chips and the low precision of PWM dead time
this paper designs a pure digital PWM waveform generator using Verilog language. This paper briefly introduces the control principle of PWM in brushless DC motor system
the relationship between motor rotor position and motor phase conduction and the PWM modulation mode
and emphatically describes the design process of PWM waveform generator using pure digital method. By adding a clock divider module
the clock frequency of dead-time counter can be increased to 16 times that of PWM counter. Two channels of PWM share a dead-time counter
saving design resources. The designed PWM waveform generator can be configured through SPI interface to realize the advantages of programmable
convenient control and so on.
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翁崇杰, 熊晓明, 马德. 一种可支持硬件触发机制的灵活可配PWM IP核的设计与实现[J]. 微电子学与计算机, 2016, 33(7): 154-158. DOI:10.19304/j.cnki.issn 1000-7180, 2016.07.034. WENG C J, XIONG X M, MA D. Design and implement of a configurable PWM IP Core with hardware trigger mechanism[J]. Microelectronics % Computer, 2016, 33(7): 154-158. DOI:10.19304/j.cnki.issn 1000-7180, 2016.07.034.
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