1. 合肥工业大学 电子科学与应用物理学院,安徽,合肥,230009
2. 河南城建学院 机构 电气与控制工程学院,河南,平顶山,467041
纸质出版:2021
移动端阅览
余振波, 聂言硕, 宋宇鲲, 侯宁. 一种自适应可重构通用浮点加速器的设计[J]. 微电子学与计算机, 2021, 38(1): 89-94.
YU Zhen-bo, NIE Yan-shuo, SONG Yu-kun, et al. Design of an adaptive reconfigurable general-purpose floating-point accelerator[J]. 2021, 38(1): 89-94.
用加速器因其专业性过强往往缺乏一定的灵活性,在处理不同类型的应用时不可避免的导致能效比的下降.本文设计了一款自适应可重构浮点加速器,它可以根据计算任务需求和可重构计算资源使用情况,在运行时将计算任务映射到可重构计算资源,具有自适应可重构的能力.该浮点加速器整体采用“RISC-V+可重构浮点运算单元”的架构,可重构浮点运算单元由一系列粗粒度浮点运算器构成,负责具体的浮点计算.该设计在Xilinx Ultrascale XCVU440FPGA芯片上进行了原型验证,结果表明,该浮点加速器具有较广的应用面,运算效率高,算法适应性强.
Application-specific accelerators often lack flexibility due to their professionalism
which inevitably leads to the decrease ofenergy efficiency during the execution of a wide range of applications. In this paper
an adaptive reconfigurable floating-point accelerator is designed
which can automatically map computing tasks to reconfigurable computing resources at runtime basing on computing task requirements and the status of reconfigurable computing resources. The floating-point accelerator uses the architecture of "RISC-V + Reconfigurable Floating-point Arithmetic Unit". The reconfigurable floating-point arithmetic unit consists of a series of coarse-grained floating-point arithmetic units
which are responsible for specific floating-point calculations.The design has been prototypical verified on the Xilinx Ultrascale XCVU440 FPGA chip
and the results show that the floating-point accelerator has wider applicability
high operation efficiency
and high algorithm adaptability.
CHEN Z Y, ZHOU H, GU J.R-accelerator: an RRAM-based CGRA accelerator with logic contraction[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(11): 2655-2667. DOI: 10.1109/TVLSI.2019.2925937.
SINGH H, LEE M H, LU G M, et al. MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications[J]. IEEE Transactions on Computers, 2000, 49(5): 465-481. DOI: 10.1109/12.859540.
HARBAUM T, SCHADE C, DAMSCHEN M, et al.Auto-SI: an adaptive reconfigurable processor with run-time loop detection and acceleration[C]//Proceedings of the 2017 30th IEEE International System-on-Chip Conference. Munich, Germany: IEEE, 2017: 153-158. DOI: 10.1109/SOCC.2017.8226027.
WIJTVLIET M, WAEIJEN L, CORPORAAL H.Coarse grained reconfigurable architectures in the past 25 years: overview and classification[C]//Proceedings of2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. Agios Konstantinos, Greece: IEEE, 2016: 235-244. DOI: 10.1109/SAMOS.2016.7818353.
BECK A C S, RUTZIG M B, CARRO L.A transparent and adaptive reconfigurable system[J]. Microprocessors and Microsystems, 2014, 38(5): 509-524. DOI: 10.1016/j.micpro.2014.03.004.
MEI B F, VERNALDE S, VERKEST D, et al. ADRES: an architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix[M]//CHEUNGP Y K, CONSTANTINIDES G A.Field Programmable Logic and Application. Berlin, Heidelberg: Springer, 2003: 61. DOI: 10.1007/b12007.
0
浏览量
39
下载量
0
CSCD
关联资源
相关文章
相关作者
相关机构
京公网安备11010602201714号