It is feasible to realize on-line test by designing an intellectual property (IP) soft core of JTAG (joint test action group) controller which is based on filed-programmable gate array (FPGA).Through analyzing the state machine of test access port (TAP) controller and the principle of some application specific integrated circuit (ASIC) for boundary scan controller

the IP soft core of JTAG controller was designed for digital signal process (DSP) which was used in an electronic engine controller (EEC).Meanwhile the hardware of testing and verification system for boundary scan was designed

and the tests of main instructions were completed.This IP soft core

which can be used in many fields such as scan test and fault injection

can load the scan vector flexibly to realize on-line test.