With the advancement of integrated circuit technology and the increasing operating frequency of circuits

the impact of Multiple-Input Switching (MIS) effects on circuit static timing analysis has become more prominent

exacerbated by process variations.Traditional Single-Input Switching (SIS) timing library construction methods struggle to handle violations of hold time and setup time.In recent years

several MIS delay models have been proposed to characterize the influence of MIS effects in timing analysis.However

most of these models overlook the impact of input switching time and load on MIS effects

resulting in pessimistic and less accurate predictions.Furthermore

these models individually model each unit without considering the relationship between MIS effects and the transistor-level topology of the unit

leading to decreased accuracy and higher characterization costs.To address these challenges

this paper proposes a novel MIS unit delay prediction framework based on heterogeneous graph neural networks.The transistor-level circuitry of multiple-input units is modeled as a heterogeneous graph

providing a comprehensive and effective representation of factors influencing MIS delay.Multiple-input gate MIS effects are trained as a unified model within this framework.In the context of the 16 nm process

the proposed model is validated on multiple-input units.The experiment results indicate that while reducing the modeling cost to 8.8% of the cost required by the ANN model

the model achieves an average error of only 1.19% for units.Compared to the ANN model

the accuracy has improved 2.05 times.