1. 智能感知与芯片安全技术实验室(天津大学),天津,300072
2. 北京智芯微电子科技有限公司,北京,100192
纸质出版:2021
移动端阅览
甄帅, 原义栋, 辛睿山, 等. Galois环振的随机重构主动屏蔽层电路[J]. 哈尔滨工业大学学报, 2021,53(6):148-154.
ZHEN Shuai, YUAN Yidong, XIN Ruishan, et al. Randomly reconfigurable active shield circuit based on Galois ring oscillator[J]. 2021, 53(6): 148-154.
甄帅, 原义栋, 辛睿山, 等. Galois环振的随机重构主动屏蔽层电路[J]. 哈尔滨工业大学学报, 2021,53(6):148-154. DOI: 10.11918/201907122.
ZHEN Shuai, YUAN Yidong, XIN Ruishan, et al. Randomly reconfigurable active shield circuit based on Galois ring oscillator[J]. 2021, 53(6): 148-154. DOI: 10.11918/201907122.
随着微电子技术的发展
集成电路安全问题已经越来越受到人们的关注.主动屏蔽层作为芯片抗侵入式攻击的核心防线
其安全性关乎集成电路的信息安全.为提高主动屏蔽层的抗攻击水平
设计了基于Galois环振的随机重构主动屏蔽层电路.首先
在主动屏蔽层中插入可重构节点
使屏蔽层走线通道间的连接关系可以随机改变
从而增加了屏蔽层的复杂性
减小其失效面积
达到屏蔽层有效抵抗重布线攻击的目的.其次
采用屏蔽层与可重构节点复用的方法
设计了一种Galois环振型真随机数发生器
解决了主动屏蔽层每次上电后状态相同的问题
进一步提高了屏蔽层的安全性.基于8通道主动屏蔽层进行了改进与实验
仿真结果表明:可重构节点在SMIC 0.18 μm工艺下面积仅 为4 395 μm2
芯片动态功耗较插入节点之前仅增加0.4%
主动屏蔽层的最大失效面积较之前缩小80%
使用真随机数作为种子生成的密码随机数序列通过了NIST SP800-22随机数测试; 采用此方法芯片功耗和面积没有明显的增加
并且可重构节点与检测电路具有占用资源小、功耗较低等优点; 电路可搭配多通道主动屏蔽层
为芯片提供较高等级的安全防护.
With the development of microelectronic technology
people pay more and more attention to the security of integrated circuits. As the main resistance for chip anti-invasive attacks
the security of active shield (AS) is concerned with the information security of integrated circuits. In this study
a random reconstruction circuit based on Galois ring oscillator was designed to improve the security level of AS. First
by inserting reconfigurable nodes into AS
the connection relationship between channels of the AS could be changed randomly. The complexity of the shield could be increased and the failure area could be reduced
which led to the effective resistance of the rerouting attack. Then
a Galois-type true random number generator was designed by reusing the reconfigurable nodes
which solved the problem that the state of the AS was consistent after each power-up and further improved the security of the shield. An experiment was designed and conducted based on the eight-channel AS. Simulation results show that the reconfigurable nodes in this study were only 4 395 μm2 using SMIC 0.18 μm process technology. The insertion of reconfigurable nodes only increased the power consumption by 0.4%
and the maximum failure area of the AS was 80% smaller. Random bit stream generated using true random number seeds passed NIST SP800-22 tests. The design circuit has the advantages of small resources occupancy and low power consumption
and it can be combined with a multi-channel AS to provide a higher level of security protection for the chip.
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