Integrated circuit chips work in complicated electromagnetic environments

which is susceptible to soft errors caused by high-energy particles. In a chip

the memory accounts for more than half of the total area

making it important to improve the reliability of the processor by hardening the memory. Therefore

a dual modular redundancy hamming (DMRH) code is designed and proposed in this paper

which can mitigate one-bit and two-bit upset in memory. First

logic optimization was carried out in the hamming code encoder to reduce the delay of the circuit

and the parity generated by this module was processed with dual modular redundancy technology

which was used as the output of the DMRH encoder. Then

the combinations of each parity and original code were processed according to the hamming decoding rules

and the revised data and two-bit upset flag were obtained. Through analysis

it was found that when the two-bit upset did not happen in the original code at the same time

the correct output could be obtained according to the two-bit upset flag. Finally

the layout segmentation technology was used to suppress the two-bit upset in the original code

which further improved the reliability of the memory. In this study

three types of DMRH codes with word lengths of 4

8

and 11 were realized. Compared with other correction codes

results show that the circuit delay of the codes obtained in this study was 85%

89%

and 96% of the eight-bit hamming code

which was lower than the BCH codes.