In order to reduce the hardware resource consumption and output delay in the conventional pipeline CORDIC (Coordinate Rotation Digital Computer) algorithm

a LUT-omitted CORDIC algorithm is proposed on the basis of the three-stage CORDIC with look-up table (LUT). The proposed new algorithm adopts 4 iterations of shifter-adder instead of LUT to reduce the register consumption apparently

and merges some iterations to decrease the output delay effectively

and guarantees the output resolution by using a combination of Binary to Bipolar Recoding (BBR) and angle range folding. The improved algorithm is specifically implemented using Verilog HDL on ISE 14.2 software platform and synthesized using XST tools

and is modeled to analyze the output errors through MATLAB. Simulation experiment results show that the register resource consumption of the new algorithm

producing sine/cosine effectively

is reduced by about 74.42% compared with the conventional one

while the output width is set to 16 equally. The computing clock periods are decreased by 68.75%

and the resolution is also improved obviously. Compared with the three-stage algorithm

the consumption of register is reduced by about 43.3%. The proposed algorithm has some advantages such as brilliant real-time performance

high resolution

and low consumption. And it is more applicable for modern digital communication systems that demand for high speed and promising real-time performance.