Aiming at the problems that time-to-digital converter(TDC)suffers a low resolution and all digital phase-locked loop(ADPLL)takes a longer time to lock reference signal

this paper proposes a fast locking ADPLL based on high precision TDC. The new TDC employs tapped delay line method and double-channel differential delay line method to improve quantization accuracy

and uses symmetric hierarchical structure to quantize negative time interval. Meanwhile

the proposed phase modulation circuit recovers quantitative pulse signal into time span signal

and advances or delays phase of feedback signal by state machine to achieve fast locking on reference signal. Moreover

it applys detection circuit of falling edge to turn off phase frequency detector and TDC

which reduce the power consumption of the entire circuit at proper time. Simulation and verification are carried out in the Xilinx KC705 development kit

and contrastive analysis on power consumption is provided between new design and traditional ADPLL based on vernier chain in Xpower software. The results show that quantization error of new ADPLL is restricted within 0.2 ns. Besides

feedback signal can rapidly lock the reference signal in three reference signal clock periods. Power consumption of the overall circuit is cut down by approximately 18.1% compared to traditional ADPLL based on vernier chain. The proposed ADPLL has the advantages of strong real-time performance

high locking speed

high quantitative precision and low power consumption

and it is more applicable for modern digital communication systems that demand for high speed and low power consumption.