With the self-development TTP/C (time trigger protocol/automotive class C) bus controller

a redundant architecture of open DEEC (digital electronic engine controller) was proposed

which was divided into three kinds of intelligent nodes: input

core calculation and output

and the task scheduling for each intelligent node was planned. Hardware platform of intelligent node was designed based on DSP (digital signal processor) and FPGA (field-programmable gate array)

and the software was designed for each intelligent node. Finally

a PIL (process in the loop) simulation test platform for open DEEC was constructed.With an engine model as the controlled object

the state regulation experiments and bus fault injection experiments were conducted.The experiment results show that the open DEEC architecture is feasible and has a good reconstruction ability.