WANG Wei-bing, XU Qian, ZHANG Hui-feng. The Design of Digital Reactor Based on CPLD and DSP[J]. 2017, 22(5): 58-64.DOI: 10.15938/j.jhust.2017.05.011.
基于 CPLD 与 DSP 的数字式电抗器的设计
摘要
为了更为准确可行地根据系统内无功状态进行抵消电力线电容效应,设计了一种可以根据系统实时运行状态平滑输出所需感性无功的数字式电抗器。该数字电抗器通过控制二次侧逆变器来改变本身电感线圈的感性电流以尽量抵消接地电容电流,从而达到动态无功补偿的目的。主 CPU 选用 DSP,并与 CPLD、A/D 相配合从而产生 PWM 以控制后续逆变电路。通过仿真和实验证明,设计的数字式电抗器具有结构简单、响应速度快、无级可调并且电感调节范围大等优点,达到了调节电力线无功平衡的作用。
Abstract
In order to counteract the transmission line capacitance effect relatively accurate based on the reactive power state of the system,this paper designs a kind of parallel digital reactor which can output the required perceptual reactive power smoothly according to the power system real-time reactive state. This digital reactor changes the inductive current which flows through the reactor’s inductance coil by controlling secondary side voltage inverter to offset the grounding capacitive current. DSP is used as CPU which is cooperated with CPLD and ADC to control the inverter output PWM. The experimental results show that digital reactor that has the advantagesof simple configuration,rapid response and wide range continuously of inductance change to reached well to adjust the action of making power penetration line reactive power balance.