一种适用于3D NAND闪存的分布式功率级LDO设计

张宁; 史维华; 王颀; 霍宗亮

doi:10.19304/J.ISSN1000-7180.2021.0959

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一种适用于3D NAND闪存的分布式功率级LDO设计

电源管理电路 | 更新时间：2026-09-04

- 一种适用于3D NAND闪存的分布式功率级LDO设计
- Distributed power stage LDO design for 3D NAND flash memory
- 微电子学与计算机 2022年39卷第3期页码：94-100
- 作者机构：
  
  1. 中国科学院大学机构,北京,101408
  2. 中国科学院机构微电子研究所,北京,100029
  3. 长江存储科技有限责任公司,湖北,武汉,430200
- 作者简介：
- 基金信息：
  
  基金项目项目编码
- DOI：10.19304/J.ISSN1000-7180.2021.0959
  中图分类号：
- 纸质出版：2022
- 稿件说明：
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张宁, 史维华, 王颀, 霍宗亮. 一种适用于3D NAND闪存的分布式功率级LDO设计[J]. 微电子学与计算机, 2022, 39(3): 94-100.

ZHANG Ning, SHI Weihua, WANG Qi, et al. Distributed power stage LDO design for 3D NAND flash memory[J]. 2022, 39(3): 94-100.
张宁, 史维华, 王颀, 霍宗亮. 一种适用于3D NAND闪存的分布式功率级LDO设计[J]. 微电子学与计算机, 2022, 39(3): 94-100. DOI： 10.19304/J.ISSN1000-7180.2021.0959.

ZHANG Ning, SHI Weihua, WANG Qi, et al. Distributed power stage LDO design for 3D NAND flash memory[J]. 2022, 39(3): 94-100. DOI： 10.19304/J.ISSN1000-7180.2021.0959.

摘要

由于3D NAND闪存芯片面积较大，其电源分布网络庞大、复杂，既需要满足多个块(block)并行读写时所需的600 mA峰值电流要求，也需要满足芯片在待机状态下的低功耗要求-针对以上问题，设计了一种为3D NAND闪存芯片进行供电的无片外电容的分布式功率级LDO电路.通过设计Active和Standby两种工作模式下的LDO进行切换以降低系统功耗；采用基于电容的升压电路驱动分布式功率级结构，适应大面积CMOS芯片的供电要求；设计了输出电压检测电路前馈控制输出级以进一步提高环路瞬态响应速度.基于长江存储工艺完成电路设计，仿真结果表明，设计的LDO的负载调整率为0.018mV/mA

带载能力达600 mA. 重载600 mA时的下冲电压为0.21V.通过流片、测试验证，设计的电路满足3D NAND闪存芯片的工作要求.

Abstract

Due to the large area of the 3D NAND flash memory chip

its power distribution network is huge and complex. It not only needs to meet the 600 mA peak current requirement when multiple blocks are read and written in parallel

but also needs to meet the low power consumption requirements of the chip in the standby. Aiming at these problems

a no off-chip capacitance LDO with distribute NMOS power stages is designed

which suits for the power supply requirement of the CMOS circuit in 3D NAND FLASH. Active/Standby mode operation is designed to reduce system power consumption. In order to enhance the driving capability and meet the requirement of power supply in large CMOS area

a boost circuit which based on switching capacitor circuit is used. The output voltage detection circuit is designed to feed forward controlling the output stage for the purpose of fast transient response. Based on the YMTC CMOS process

the circuit design is completed. The simulation results show that the designed LDO achieves 600 mA load capability with 0.018mV/mA load regulation. The undershoot voltage is 0.21V under 600mA loading current.

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references

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程立, 黄鲁. 一种高性能无片外电容型LDO设计[J]. 微电子学与计算机, 2017, 34(10): 119-122. DOI: 10.19304/j.cnki.issn1000-7180.2017.10.025. CHENG L, HUANG L. Design of a high performance output-capacitorless LDO[J]. Microelectronics % Computer, 2017, 34(10): 119-122. DOI: 10.19304/j.cnki.issn1000-7180.2017.10.025.

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