Base on the analysis of preamplifier latch comparator

there is a high speed high resolution CMOS comparator presented.The comparator uses negative resistors in parallel with load transistors to improve the gain of preamplifier

in order to reduce offset voltage.Meanwhile

the comparator uses a preset quiescent current to improve the regenerative speed.Fabricated in TSMC 0.18 μm process model

it is simulated with Cadence specture.The simulated results show the clock could be as high as 1GSPS

the resolution is 0.6 mV

delay time is 320 ps

and power consumption is 1 mW.