The hearing compensation algorithm and noise reduction algorithm in multi-channel digital hearing aids were studied in this paper

and a low-power VLSI design according to these algorithms was implemented further.On hearing compensation

a new multi-channel Wide Dynamic Range Compression(WDRC) algorithm was proposed

which can not only reduce the cost of storage and calculation.On noise reduction

by considering the correlation between adjacent frames of speech spectrum and noise spectrum

the traditional multi-band spectral subtraction algorithm was modified for parallel operation in hardware implementation

without degrading the performance.The low-power VLSI design of a multi-channel digital hearing aid based on the proposed algorithms was realized in SMIC 130nm process.The post-simulation power dissipation of the system is only 228 μW.