Design methods of the digital costas loop based on field programmable gate array (FPGA) was studied. First

the structure and performance of the digital costas loop based on the model of phase -locked loop was studied and a detailed analysis of the digital costas loop was presented. Then

all parameter formulas were derived accurately and some important formulas were modified in order to improve the performance of digital costas loop. Finally

each module of the costas loop was developed by Verilog HDL on a Xilinx FPGA

and all function blocks were assembled into a complete costas loop.Combined with an actual case

the register transfer logic (RTL) schematic of the digital costas loop which has been implemented on FPGA is displayed

and the simulation results are shown.The simulation data shows that the digital costas loop with practical and excellent performance can be achieved according to the design method and formulas presented by this paper.