A dual-loop half-rate clock and data recovery circuit (CDR) used in 2.5Gb/s high-speed transceiver is designed with SMIC 0.18m CMOS technology.The phase-locked loop provides 16-phase

1.25 GHz reference clocks with same phase interval to CDR loop.The CDR loop consists of 1:2demultiplexer designed in current mode logic

clock recovery circuit with an innovative phase interpolation and selection technology

lead-lag sampling phase detector which can eliminate meta-stable state

and precision preseted digital filter with the phase selection algorithm of binary search and sequential search.The proposed circuit is verified with digital/analog mixed simulator SpectreVerilog and the results show that the circuit can process the 2.5Gb/s differential data reliably to accomplish clock recovery and data retiming.