As the device dimension scales into the nanometer era

the read-out circuits suffer from slow read speed or low yield for the reduced bit-line current and device mismatches.The proposed CMOS Current-Sampling-Based SA can overcome the effect of the device mismatches and operate correctly at a desired speed even if the bit-line current is very weak.The circuit is realized in Silterra 0.13m C13 GCMOS technology and simulation results show that the random read-out can be finished in 4ns when the supply voltage is 0.8V with the cell current and reference current are 150 nA and 100 nA

respectively.