In this paper a SystemC based cycle-accurate model for Reconfigurable Application Specific Processor is presented. The model uses a modular design

based on SystemC transaction-level modeling

separating the communications functions and the computing functions

and the communication between modules is achieved through function calls. The model provides a simulation platform for the Reconfigurable Application Specific processor core

compared with the traditional RTL verification methods

greatly improving the efficiency of the processor core simulation.