This paper presents a digitally controlled oscillator (DCO) based on a multiplying delay locked loop (MDLL)

and a DCO-based configurable digital frequency synthesizer (DFS) is implemented. The output clock frequency is equal to the reference clock frequency multiplied by divided by . The multiplication ratio and division ratio can be programmed from 2 to 32

and 1 to 32

respectively. The frequency synthesizer achieves similar jitter performance as conventional MDLL. The DFS is implemented in TSMC 0.13-μm CMOS technology

with a layout area of 480 μm×120 μm. The frequency range of the input and output clock are 1~270 MHz and 15~400 MHz

respectively. The measured phase noise is -110.01 dBc/Hz@1 MHz

when the output clock frequency is 270 MHz.