Flash型FPGA单粒子瞬态脉冲分段滤除电路设计

史方显; 曾立; 王淼; 曹建勋; 权妙静

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Flash型FPGA单粒子瞬态脉冲分段滤除电路设计

更新时间：2026-09-04

- Flash型FPGA单粒子瞬态脉冲分段滤除电路设计
- Segmented Filtering Circuit for SET Pulse in Flash-based FPGAs
- 微电子学与计算机 2016年33卷第2期页码：64-68
- 作者机构：
  
  北京航空航天大学宇航学院,北京,100191
- 作者简介：
- 基金信息：
  
  国家自然科学基金 41274190国家自然科学基金 41074130国家自然科学基金 41327802
- DOI：
  中图分类号：
- 纸质出版：2016
- 稿件说明：
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史方显, 曾立, 王淼, 曹建勋, 权妙静. Flash型FPGA单粒子瞬态脉冲分段滤除电路设计[J]. 微电子学与计算机, 2016, 33(2): 64-68.

SHI Fang-xian, ZENG Li, WANG Miao, et al. Segmented Filtering Circuit for SET Pulse in Flash-based FPGAs[J]. 2016, 33(2): 64-68.
史方显, 曾立, 王淼, 曹建勋, 权妙静. Flash型FPGA单粒子瞬态脉冲分段滤除电路设计[J]. 微电子学与计算机, 2016, 33(2): 64-68. DOI：

SHI Fang-xian, ZENG Li, WANG Miao, et al. Segmented Filtering Circuit for SET Pulse in Flash-based FPGAs[J]. 2016, 33(2): 64-68. DOI：

摘要

为提高FPGA在辐射环境条件下的抗单粒子脉冲(SET)的能力

设计了一种由多个延时单元和并联逻辑保护单元(Guard Gate

GG)构成的SET脉冲分段滤除电路.将SET脉冲处理延时减小至传统方法的10.42%~49.8%

从而提高电路对SET脉冲的处理能力

同时占用的逻辑资源未有明显增加.

Abstract

A segmented filtering circuit with delay units and guard gates is proposed to filter SET pulses with different width

considering the range and distribution of SET pulse widths produced in FPGA and the propagation induced pulse broadening. Dividing the widths of SET pulses into several intervals

parallel guard gates with different delay buffers generate corresponding results to different intervals. According to the results

this circuit selects the output in the shortest time

improving the performance on dealing with SET pulses. Simulation results in Fusion family flash-based FPGA indicate that

compared to traditional methods

the segmented filtering circuit can cut the filtering delay of SET pulse in critical path down to 10.42%~49.8%

while power consumption decreasing and no hardware resource increase.

关键词

Keywords

references

梁斌, 陈书明, 刘必慰, 等. SET传播过程中的脉冲展宽效应[J]. 半导体学报, 2008, 29(9): 1827-1831. DOI: 1827

Lopez-Ongil C, Department E T, Madrid U C I D, et al. Logic masking for SET mitigation using approximate logic circuits[C]// On-Line Testing Symposium (IOLTS), 2012 IEEE 18th International. Spain, Sitges, 2012, 7203(4): 176-181.

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黄晔. 同时针对SEU/SET/MBU的MOS集成电路抗辐射加固技术研究[D]. 上海: 上海交通大学, 2009.

费尔南达·利马·卡斯腾斯密得. 基于SRAM的FPGA容错技术[M]. 北京: 中国宇航出版社, 2009.

Wirth G, Kastensmidt F L, Ribeiro I. Single event transients in logic circuits-oad and poropagation induced pulse broadening[J]. Nuclear Science, IEEE Transactions on, 2008, 55(6): 2928-2935. DOI: 2928

Violante M. On the evaluation of radiation-induced transient faults in flash-based FPGAs[C]//On-Line Testing Symposium, IOLTS '08. 14th IEEE International. Greece, Rhodles, IEEE, 2008: 135-140.

Rezgui S, Wang J J, Tung E C, et al. New mjethodologies for SET characterization and mitigation in flash-based FPGAs[J]. Nuclear Science, IEEE Transactions on, 2007, 54(6): 2512-2524. DOI: 2512

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