Balasubramanian A, Bhuva B L, Black J D, et al. RHBD techniques for mitigating effects of single-event hits using guard-gates[J]. IEEE Transactions on Nuclear Science, 2006, 52(6): 2531-2535. DOI: 2531

Chang M F, Yang S M, Chen K T, et al. Wide-VDD embedded asynchronous SRAM with dual-mode self-timed technique for dynamic voltage systems[J]. IEEE Transactions on Circuits and Systems-Ⅰ, 2009, 56(8): 657-667. DOI: 657

Amusan O A, Massengill L W, Bhuva B L, et al. Design techniques to reduce SET pulse widths in deep-submicron combinational logic[J]. IEEE Transactions on Nuclear Science, 2007, 54(6): 2060-2064. DOI: 2060

Karandikar A, Parhi K K. Low power SRAM design using hierarchical divided bit-line approach[C]//International Conference on Computer Design: VLSI in Computers % Processors. Austin, Texas, USA: IEEE, 1998: 82-88.

Chang M F, Yang S M, Chen K T, et al. Improving the speed and power of compilable SRAM using dual-mode self-timed technique[C]//IEEE International Workshop on Memory Technology, Design and Testing. Taipei, China: IEEE Computer Society, 2007: 57-60.

Sinangil M E, Verma N, Chandrakasan A P. A reconfigurable 8T ultra-dynamic voltage scalable (U-DVS) SRAM in 65 nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2009, 44(11): 3163-3173. DOI: 3163

Calin T, Nicolaidis M, Velazco R. Upset hardened memory design for submicron CMOS technology[J]. IEEE Transactions on Nuclear Science, 1997, 43(6): 2874-2878. DOI: 2874

Amrutur B S, Horowitz M A. A replica technique for wordline and sense control in low-power SRAM's[J]. IEEE Journal of Solid-State Circuits, 1998, 33(8): 1208-1219. DOI: 1208