青岛理工大学 机构 , 通信与电子工程学院,山东,青岛,266033
纸质出版:2016
移动端阅览
聂廷远, 李坤龙, 高久顼. 布图规划约束对VLSI设计性能的影响[J]. 微电子学与计算机, 2016, 33(11): 104-108.
NIE Ting-yuan, LI Kun-long, GAO Jiu-xu. The Influence on VLSI Design Performance by Constraints in Floorplanning[J]. 2016, 33(11): 104-108.
布图规划处于芯片物理设计的前端
对VLSI整体性能起着至关重要的作用.给出了平面布图规划约束的介绍
通过在布图规划阶段进行约束嵌入的实验
考查了约束对VLSI布图规划设计性能的影响.在IBM-HB+ Benchmark Suites上嵌入约束的实验表明
约束设置会给VLSI布图规划带来一定的影响
甚至会改善设计质量.
The floorplanning plays a vital role to the final VLSI performance because it is in the earlier stage of the physical design. In this paper
we introduce several kinds of constraints in floorplanning. We investigate the influence caused by constraint in floorplanning. The experimental results on IBM-HB+ Benchmark Suites show that the constraint embedding had some influence on the floorplanning design
sometimes it may improve the quality of the design.
Murata H, Fujiyoshi K, Nakatake S, et al. VLSI module placement based on rectangle-packing by the sequence-pair[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997, 15(12): 1518-1524. DOI: 1518
Young E F Y, Chu C CN, Ho M L. Placement constraints in floorplan design[J]. IEEE Transactions on Very Large Scale Integration Systems, 2004, 12(7): 735-745. DOI: 735
Adya S N, Markov I L. Fixed-outline floorplanning: enabling hierarchical design[J]. IEEE Transactions on Very Large Scale Integration Systems, 2003, 11(6): 1120-1135. DOI: 1120
Young F Y, Wong D F. Slicing floorplans with pre-placed modules[C]//Proc of IEEE/ACM international conference on Computer-aided design. San Jose, Nevada, USA: IEEE, 1998: 252-258.
NgA N, Markov I L, Aggarwal R, et al. Solving hard instances of floorplacement[C]//Proc of ISPD '06. San Jose California, USA: IEEE, 2006: 170-177.
Wu GM, Wu S W, Chang Y W, et al. B*-Trees: a new representation for non-slicing floorplans[C]//Proc of ACM/IEEE Design Automation Conference. LOS Angeles, California, USA: IEEE, 2000: 458-463.
Yan J Z, Viswanathan N, Chu C. An effective floorplan-guided placement algorithm for large-scale mixed-size designs[J]. ACM Transactions on Design Automation of Electronic Systems, 2014, 19(3): 1-25. DOI: 1
Ma Y, Dong S, Hong X, et al. VLSIfloorplanning with boundary constraints based on corner block list[C]//Proc of Design Automation Conference. Las Vegas, Nevada, USA: IEEE, 2001: 509-514.
Ma Y, Hong X, Dong S, et al. Floorplanning with abutment constraints based on corner block list[J]. Integration the VLSI Journal, 2001, 31(1): 65-77. DOI: 65
Tang X, Wong D F. Floorplanning with alignment and performance constraints[C]//Proc of the 39th annual Design Automation Conference. New Orleans, USA: IEEE, 2002: 848-853.
罗佐, 杜世民, 戚利侠, 等. 基于快速模拟退火算法的可切割布图规划方法[J]. 微电子学与计算机, 2012, 29(9): 109-112. DOI: 109
郝冬艳, 张明, 郑伟. 低功耗VLSI芯片的设计方法[J]. 微电子学与计算机, 2007, 24(6): 137-139. DOI: 137
0
浏览量
10
下载量
0
CSCD
关联资源
相关文章
相关作者
相关机构
京公网安备11010602201714号