应用于14bit低功耗流水线ADC的sub-ADC电路设计

陈忠学; 何全; 章国豪

Chinese

您当前的位置：

首页 >

文章列表页 >

应用于14bit低功耗流水线ADC的sub-ADC电路设计

更新时间：2026-09-04

- 应用于14bit低功耗流水线ADC的sub-ADC电路设计
- Design of Sub-ADC Applied to 14 Bit Low-Power Pipeline ADC
- 微电子学与计算机 2017年34卷第1期页码：132-135
- 作者机构：
  
  广东工业大学机构信息工程学院,广东,广州,510006
- 作者简介：
- 基金信息：
- DOI：
  中图分类号：
- 纸质出版：2017
- 稿件说明：
移动端阅览
陈忠学, 何全, 章国豪. 应用于14bit低功耗流水线ADC的sub-ADC电路设计[J]. 微电子学与计算机, 2017, 34(1): 132-135,140.

CHEN Zhong-xue, HE Quan, ZHANG Guo-hao. Design of Sub-ADC Applied to 14 Bit Low-Power Pipeline ADC[J]. 2017, 34(1): 132-135.
陈忠学, 何全, 章国豪. 应用于14bit低功耗流水线ADC的sub-ADC电路设计[J]. 微电子学与计算机, 2017, 34(1): 132-135,140. DOI：

CHEN Zhong-xue, HE Quan, ZHANG Guo-hao. Design of Sub-ADC Applied to 14 Bit Low-Power Pipeline ADC[J]. 2017, 34(1): 132-135. DOI：

摘要

基于SMIC 0.18m标准CMOS工艺

设计了一种应用于14bit、100 MHz采样频率低功耗流水线ADC的1.5位sub-ADC单元电路.sub-ADC主要包括核心模块比较器电路和编码单元电路.采用由前置放大器和锁存器构成的动态锁存比较器

来实现较高的速率.为降低流水线ADC的每一级功耗

提出一种新结构的sub-ADC电路

实现前置放大器在相邻的比较器中共享

增加复位开关电路降低“回踢”噪声和消除两锁存器之间的相互干扰.仿真结果表明:在3V电源电压、100 MHz的采样频率下

输入输出正确翻转

传输延时为1.73ns

功耗为157.3A

可满足高精度低功耗流水线ADC的性能要求.

Abstract

Design of the 1.5bit sub-ADC applied to 14 bit low-power pipeline ADC circuit.The circuit is fabricated in a 0.18m standard CMOS process provided by SMIC.The sub-ADC mainly includes the core module comparator circuit and the encoder circuit.The high speed is realized by using the dynamic latch comparator which is composed of the preamplifier and the latch.In order to reduce the power consumption of pipelined ADC

a new structure of sub-ADC circuit is proposed

which can realize the sharing of the preamplifier in the adjacent comparator.Increase the reset switch circuit to reduce Kickback noise and eliminate the mutual interference between the two latches.The simulation results show that the input and output correct flip in 100 MHz sampling frequency at 3Vsupply voltage.The transmission delay is 1.73 ns

and the power consumption is 157.28 uA.Can meet the high accuracy and low power pipeline ADC performance requirements.

关键词

Keywords

references

Hwi-Cheol K, Deog-Kyoon J, Kim W. A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters[J]. IEEE Transactions on Circuits and Systems I-regular Papers, 2006, 53(4): 795-801. DOI: 795

Haze J, Fujcik L, Sajdl O. Modeling of 10bit 40MHza low power pipelined ADC utilizing novel background[C]//International Conference on Systems%amp;amp;International Conference on International Conference on Networking. HongKong, 2006: 180-181.

Jonsson B E, Tenhunen H. A low-voltage 32 MSample/s parallel pipelined switched-current ADC[J]. Electronics Letters, 1998, 34(20): 1906-1907. DOI: 1906

王刚. 14位100-MS/s流水线ADC低功耗设计[D]. 杭州: 浙江大学, 2013: 14-27.

Razavi B. 模拟CMOS集成电路设计[M]. 西安. 西安交通大学出版社, 2003.

贾华宇. 高性能流水线模数转换及其数字校准技术研究[M]. 西安. 西安电子科技大学出版社, 2014.

Sounak R, Sanjoy KD, Swapna B. A parallel pipeline ADC with a Sub-ADC employing an improvized dynamic comparator[C]//IEEE Region 10Conference. IEEE, 2009: 1-6.

Robert L, Markus K, Frank O. Implementation of a high-speed flash ADC for high-performance pipeline ADCs in an 180nm CMOS process[C]//IEEE 2015ISPACS. Barli, 2015: 317-322.

Wei-Hsuan T, Tzung-Hung K. A 1.2V 30mW 8b800MS/s Time-interleaved ADC in 65nm CMOS[C]//IEEE Symposium on VLSI Circuits. Honolulu, 2008: 18-20.

周佳宁, 李荣宽. 一种低功耗14位10MS/s流水线A/D转换器[J]. 微电子学与计算机. 2012, 29(4): 49-57. DOI: 49

浏览量

下载量

CSCD

文章被引用时，请邮件提醒。

提交

工具集

关联资源

一种低温漂低功耗RC振荡器的设计

适用于生物电信号采集的低功耗10 bit 40 KS/s SAR ADC设计

一种低噪声的斩波电流反馈仪表放大器

一种低电压低功耗射频接收前端电路的设计

1.3~2.2 GHz低噪声低功耗CMOS LC VCO的设计