LOD效应和WPE效应在纳米工艺PDK中的应用

周欢欢; 陈岚; 尹明会; 王晨; 张卫华

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LOD效应和WPE效应在纳米工艺PDK中的应用

更新时间：2026-09-04

- LOD效应和WPE效应在纳米工艺PDK中的应用
- The Apply of LOD Effects and WPE Effect in Nanometer Process PDK
- 微电子学与计算机 2019年36卷第2期页码：1-5
- 作者机构：
  
  1. 中国科学院机构微电子研究所,北京,100029
  2. 三维及纳米集成电路设计自动化技术北京市重点实验室,北京,100029
- 作者简介：
- 基金信息：
  
  国家03重大专项资助项目 2018ZX03001007-003北京市技术专项资助项目 Z171100001117147
- DOI：
  中图分类号：
- 纸质出版：2019
- 稿件说明：
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周欢欢, 陈岚, 尹明会, 王晨, 张卫华. LOD效应和WPE效应在纳米工艺PDK中的应用[J]. 微电子学与计算机, 2019, 36(2): 1-5.

ZHOU Huan-huan, CHEN Lan, YIN Ming-hui, et al. The Apply of LOD Effects and WPE Effect in Nanometer Process PDK[J]. 2019, 36(2): 1-5.
周欢欢, 陈岚, 尹明会, 王晨, 张卫华. LOD效应和WPE效应在纳米工艺PDK中的应用[J]. 微电子学与计算机, 2019, 36(2): 1-5. DOI：

ZHOU Huan-huan, CHEN Lan, YIN Ming-hui, et al. The Apply of LOD Effects and WPE Effect in Nanometer Process PDK[J]. 2019, 36(2): 1-5. DOI：

摘要

本文研究了自主开发的40 nm工艺PDK中的LOD效应和WPE效应.LOD参数SA和WPE参数left影响CMOS器件特性

尤其饱和电流I和阈值电压V.随着SA减小

NMOS的I减小4.25%而V增大2.79%;PMOS的电参数与SA关系曲线与NMOS的一致

但比NMOS趋势要强

I减小8.32%而V增大6.78%;并解释了LOD效应的物理机制.随着left的减小

NMOS的I减小9.03%而V增大12.5%;PMOS的电参数与left关系曲线比NMOS的要弱

I减小8.50%而V增大4.61%

并提出了WPE效应下器件电参数变化原因.在纳米工艺PDK中

LOD效应和WPE效应的准确应用可以更好地模拟器件性能并改善电路设计精度.

Abstract

In this paper

We research LOD and WPE effects of self-developed 40nm process PDK.The parameter SA of LOD effect and the parameter left of WPE effect influence the characteristics of CMOS device

especially the saturation current I and the threshold voltage V. With the decrease of SA

I of NMOS decreases by 4.25% and V increases by 2.79%.The relationship between electrical parameters and SA of PMOS is consistent with that of NMOS

but the trend is stronger than NMOS

I decreases by 8.32% and V increases by 6.78%. The physical mechanism of LOD effect is explained.With the decrease of left

the I of NMOS decreases by 9.03% and V increases by 12.5%.The relationship between the electrical parameters of PMOS and left is weaker than that of NMOS

I decreases by 8.50%

and V increases by 4.61%.The cause that the electrical parameters change under WPE effect is proposed. In the nanometer process PDK

the accurate application of LOD and WPE effects can better simulate device performance

and improve the precision of circuit.

关键词

Keywords

references

C. Ndiaye, V. Huard, R. Bertholon, et al. Layout Dependent Effect: Impact on device performance and reliability in recent CMOS node[C]// 2016 IEEE International Integrated Reliability Workshop (IIRW). South Lake Tahoe, CA, USA : IEEE, 2016: 24-28.

Zhang Y, Liu B, Yang B, et al. CMOS Op-amp circuit synthesis with geometric propramming models for layout-dependent effects [C]// Thirteenth International Symposium on Quality Electronic Design (ISQED). Santa Clara, CA, USA: IEEE, 2012: 464-469.

Li R Y, Tao J J, Yang T, et al. A systematic study of layout proximity effects for 28nm Poly/SiON logic technology [C]// China Semiconductor Technology International Conference (CSTIC). Shanghai, China: IEEE, 2015: 1-4.

P.G.Drennan, M.L.Kniffin, D.R.Locascio. Implications of proximity effects for analog design[C]// IEEE Custom Integrated Circuits Conference. San Jose, CA, USA: IEEE, 2006: 169-176.

SMIC. TD-LO28-SP-2001. 28nm Poly SiON Low Power 1P10M 1.05V/1.8V SPICE Model(Version 1.1) [S]. Joe Li, Aug 2008: 49-54.

Hung-Chih Ou, Kai-Han Tseng, Jhao-Yan Liu, et al. Layout-Dependent Effects-Aware Analytical Analog Placement[J]. IEEE Transactions on Computer-Aided design of integrated circuits and systems, 2016, 8(35): 1243-1254. DOI: 1243

Yi-Ming Sheu, Ke-Wei Su, Shiyang Tian, et al. Modeling the Well_Edge Proximity Effect in Highly Scaled MOSFETs[J]. IEEE Transactions on Electron Devices, 2006, 11(53): 831-834. DOI: 831

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