1. 北方工业大学 机构 电子信息工程学院,北京,100144
2. 中国科学院 机构 微电子研究所,北京,100029
纸质出版:2018
移动端阅览
秦明龙, 魏淑华, 武锦, 吴旦昱. 超高速时间交织ADC通道失配后台校准算法[J]. 微电子学与计算机, 2018, 35(11): 8-12.
QIN Ming-long, WEI Shu-hua, WU Jin, et al. Background Calibration Algorithm for Channel Mismatch of Super High Speed Time-Interleaved ADC[J]. 2018, 35(11): 8-12.
为了消除多通道时间交织模数转换器(TIADC)三种主要失配误差:通道间的失调失配误差、通道间的增益失配误差及通道间的采样时间失配误差
提出了一种片内数字电路后台校准算法.该算法通过增加一路参考ADC和统计累加的方式
在后台将待校准通道和参考通道的输出作相关运算以提取出误差信息
再通过模拟电路对失配误差进行迭代补偿
从而达到校准的目的.将此算法应用到12位3 GS/s四通道TIADC电路模型中
当输入信号归一化频率/=0.165 69时
校准后
ENOB和SNR分别从4.176 5 bits和26.812 8 dB提高到11.699 3 bits和72.102 3 dB
校准效果明显.验证了该后台数字校准算法的有效性.此外
此算法对输入信号类型
输入频率及通道间校准顺序没有严格限制
可以扩展到任意通道数.
To eliminatethe three main mismatch errors of themulti-channel time-interleavedanalog-to-digitalconverter (TIADC)
which are offset mismatch errorbetweenchannel
channel gain mismatch error and sampling time mismatch errorof channel
a background calibration algorithmfor in chip digital circuits isproposed.By adding a way of reference ADC and statistical accumulation
the algorithms perform correlation operation on the output of the calibrated channel and reference channel in order to extract the error information in the background
and then iterates compensation for the mismatch errors through the analog circuit
so as to achieve the purpose of calibration.The algorithm is applied to the 12 bits 3 GS/s four channels TIADC model circuit.When the normalized frequency of input signal is /=0.16569
after calibration
the ENOB and SNR increase from 4.176 5 bits and 26.812 8 dB to 11.699 3 bits and 72.102 3 dB
respectively
and the calibration effect is obvious.In addition
the algorithm is not strictly limited to input signal type
input frequency and inter channel calibration order
and can be extended to any number of channels.
Wei Hegong, Zhang Peng, Bibhu Datta Sahoo, et al.An 8bits 4GS/s 120 mw CMOS ADC [J].IEEE Journal of Solid-State Circuits, 2014, 49(8):1751-1761. DOI: 1751
邓红辉, 刘言言, 陈红梅.时间交织ADC时间失配后台数字校准算[J].微电子学, 2016, 46(4):542-546. DOI: 542
王晓蕾, 王玉莹.基于过零检测的ADC时钟失配校准算法[J].微电子学与计算机, 2016, 34(5):72-79. DOI: 72
Jama S M, Sing D F M P, Hurst P J, et al. Calibration of samplel-Time error in two-channel time interleaved analog converter[J]. IEEE Transaction on Circuit and Systems, 2004, 51(1):130-139. DOI: 130
尹生勇, 潘云胜, 陈红梅.一种时间交织ADC的时间失配后台校准算法[J].华中科技大学学报(自然科学版), 2016, 44(2):56-60. DOI: 56
叶凡.多通道时间交织模数转换器的校准与集成电路实现方法研究[D].上海: 复旦大学, 2010.
0
浏览量
47
下载量
0
CSCD
关联资源
相关文章
相关作者
相关机构
京公网安备11010602201714号