一种基于预判机制的极化码译码算法及VLSI架构

杜高明; 胡国庆; 林青; 张多利; 宋宇鲲; 欧阳一鸣

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一种基于预判机制的极化码译码算法及VLSI架构

更新时间：2026-09-04

- 一种基于预判机制的极化码译码算法及VLSI架构
- A polar code decoding algorithm based on pre-judgment mechanism and its VLSI architecture
- 微电子学与计算机 2019年36卷第12期页码：11-15
- 作者机构：
  
  合肥工业大学电子科学与应用物理学院,合肥,230009
- 作者简介：
- 基金信息：
  
  国家自然科学基金 61474036教育部IC设计网上合作研究中心 JSGG20170413153845042
- DOI：
  中图分类号：
- 纸质出版：2019
- 稿件说明：
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杜高明, 胡国庆, 林青, 张多利, 宋宇鲲, 欧阳一鸣. 一种基于预判机制的极化码译码算法及VLSI架构[J]. 微电子学与计算机, 2019, 36(12): 11-15, 20.

DU Gao-ming, HU Guo-qing, LIN Qing, et al. A polar code decoding algorithm based on pre-judgment mechanism and its VLSI architecture[J]. 2019, 36(12): 11-15.
杜高明, 胡国庆, 林青, 张多利, 宋宇鲲, 欧阳一鸣. 一种基于预判机制的极化码译码算法及VLSI架构[J]. 微电子学与计算机, 2019, 36(12): 11-15, 20. DOI：

DU Gao-ming, HU Guo-qing, LIN Qing, et al. A polar code decoding algorithm based on pre-judgment mechanism and its VLSI architecture[J]. 2019, 36(12): 11-15. DOI：

摘要

本文提出一种基于对数似然比的预判机制

根据每层对数似然比符号直接判决分裂成"1"或者"0"和固定比特层直接分裂成已知比特

旨在减少路径分裂以及通过直接继承上一层路径度量值的方式

移除冗余的路径度量值计算.基于该机制

我们设计码长=1 024

码率=0.5

列表宽度=2的VLSI硬件架构.实验结果表明

其工作频率在384 MHz下

能达到约160 Mbps的吞吐率

延迟降低约51%.

Abstract

This paper proposes a pre-judgment mechanism based on log-likelihood ratio

reducing redundant split for SCL (RRS-SCL). According to the log-likelihood ratio symbol decision of each layer

it is split into "1" or "0" and the fixed bit layer are directly split into known bits

which aims to reduce path splitting and remove redundant path metric calculations by directly inheriting the path metrics from the previous layer. Based on the scheme

we design RRS-SCL VLSI architecture with code length N=1024

the code rate R=0.5

and the list width L=2. The experimental results show that the throughput can be achieved at 160Mbps under 384MHz and delay is reduced by approximately 51%.

关键词

Keywords

references

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