西南科技大学 机构 信息工程学院,四川,绵阳,621010
纸质出版:2019
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鄂长江, 李少甫, 齐艺轲. 单粒子多瞬态诱导的组合电路软错误敏感性评估[J]. 微电子学与计算机, 2019, 36(11): 16-19.
E Chang-jiang, LI Shao-fu, QI Yi-ke. Soft error sensitivity estimation of single event multi-transient induced combination circuits[J]. 2019, 36(11): 16-19.
为了评估数字电路的软错误敏感性
研究了一种适于FPGA的单粒子多瞬态(SEMT)诱导的组合电路软错误评估方法.考虑脉冲传输过程中受到的电气屏蔽的影响和辐射粒子入射的随机性
控制不同脉宽的SEMT脉冲对所有SEMT故障位置进行故障注入
统计错误结果.实验结果表明
该方法能对单粒子两个及以上瞬态诱导的组合电路软错误敏感性进行分析
得到各故障位置敏感度信息
供电路设计前端参考改进.
In order to evaluate the soft error sensitivity of digital circuits
a single event multi-transient (SEMT) induced soft error analysis system for combinational circuits based on FPGA is proposed. Considering the influence of electrical shielding and the randomness of incident radiation particles in the process of pulse transmission
we control the different pulse width of the SEMT pulse to inject all the fault locations of the SEMT
and statistics the error results. The experimental results show that the system can analyze the soft error sensitivity of two or more transient induced combinational circuits. The sensitivity information of each fault location can be obtained
and the front-end of power supply circuit design can be improved.
MAHESHWARI A. Techniques for transient fault sensitivity analysis and reduction in VLSI circuits[C]// IEEE International Symposium on Defect % Fault Tolerance in Vlsi Systems. Boston, Massachusetts, USA, IEEE, 2003.
RAO R R, CHOPRA K, BLAAUW D T, et al. Computing the soft error rate of a combinational logic circuit using parameterized descriptors[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007, 26(3):468-479. DOI: 468
MAVIS D G, EATON P H. SEU and SET modeling and mitigation in deep submicron technologies[C]// Reliability Physics Symposium, 2007. Phoenix, USA, IEEE International. IEEE, 2007: 293-305.
SHIVAKUMAR P. Modeling the effect of technology trends on the soft error rate of combinational logic[C]// Proceedings of the 2002 International Conference on Dependable Systems and Networks. Washington, D.C., USA, IEEE, 2002.
ENTRENA L, GARCIA-VALDERAS M, FERNANDEZ-CARDENAl R, et al. Soft error sensitivity evaluation of microprocessors by multilevel emulation-based fault injection[J]. IEEE Transactions on Computers, 2012, 61(3):313-322. DOI: 313
REVIRIEGO P, MAESTRO J A, CERVANTES C. Reliability analysis of memories suffering multiple bit upsets[J].IEEE Transactions on Device % Materials Reliability, 2007, 7(4):592-601. DOI: 592
梁华国, 袁德冉, 闫爱斌, 等.考虑单粒子多瞬态故障的数字电路失效概率评估[J].计算机辅助设计与图形学学报, 2016, 28(3):505-512. DOI: 505
周婉婷, 靳丽娜, 叶世旺.单粒子瞬态效应硬件注入模型实现和仿真[J].微电子学与计算机, 2014, 31(9):84-87. DOI: 84
武振平, 付方发, 肖立伊.基于VHDL故障注入的处理器敏感性分析[J].微电子学与计算机, 2012, 29(10):51-54. DOI: 51
HARADA R, MITSUYAMA Y, HASHIMOTO M, et al. Neutron induced single event multiple transients with voltage scaling and body biasing[J]. IEEE International Reliability Physics Symposium, 2013, 470(9):3C.4.1-3C.4.5. DOI: 3C.4.1
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