JOSHI G, SINGH D, THANGJAM S. Effect of temperature variation on gate tunneling currents in nanoscale MOSFETs [C]//Proc IEEE Conf Nanotechnology. China, Xi′an, 2008: 37.

CHENG Y C, KER M D. The effect of IEC-like fast transients on RC-triggered ESD power clamps [J]. IEEE Trans Electron Devices, 2009(56):1204. DOI: 1204

KER M D, CHEN T Y. ESD protection design on analog pin with very low input capacitance for highfrequency or cur rentmode applications [J]. IEEE J. Solid-State Circuits, 2000, 35(8): 1194-1199. DOI: 1194

CHIU P Y, KER M D. New low-leakage power-rail ESD clamp circuit in a 65-nm low-voltage CMOS process [J]. IEEE Trans Device Mater Reliab, 2011, 11: 474. DOI:10.1109/tdmr.2010.2066976.

STOCKINGER M, MILLER J W, KHAZHINSKY M G, et al. Boosted and distributed rail clamp networks for ESD protection in advanced CMOS technologies [C] //Proc EOS/ESD Symp. [S.l], 2003: 17.

SMITH J, CLINE R, BOSELLI G. A low leakage low cost PMOS-based power supply clamp with active feedback for ESD protection in 65-nm CMOS technologies[C] //Proc EOS/ESD Symp. [S.l], 2005: 298-306.

CAI X W. An area-efficient clamp based on transmisssion gate feedback technology for power rail electrostatic discharge protection [J]. IEEE Electron Device Letters, 2015, DOI: 10.1109/LED.2015.2434835.

KER M D, CHIU P Y, TSAI F Y, et al. On the design of power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process [J]. IEEE Int Symp Circuits Syst, 2009: 2281. DOI:10.1109/ISCAS.2009.5118254.

YEH C T, KER M D. Capacitor-less design of power-rail ESD clamp circuit with adjustable holding voltage for on-chip ESD protection [J]. IEEE J Solid-State Circuits, 2010(45):2476. DOI: 2476