A system-on-chip (SoC) has been developed in this study to cater to various applications requiring high-performance processing and low power consumption

such as recognition

in-ference

measurement

control

and security.The SoC integrates three synthesizable processors:eight CPUs (M32R)

two multi-bank matrix processors (MBMX)

and one controller (M32C).These processors operate at frequencies of 1 GHz

500 MHz

and 500 MHz respectively.The three processors are interconnected on the chip through a high-bandwidth multi-layer system bus.The eight CPUs are connected to a shared pipeline bus via a cache coherence mechanism.Additionally

the eight CPUs share a 512 KB L2 cache to reduce internal bus traffic.The multi-bank matrix processor

which features 2-read-1-write computation and background I/O operations

is implemented using a 1 GHz CPU and a delay management network.This network includes a delay monitor applicable to any application or process technology.The configurable heterogeneous architecture comprises nine CPUs and two matrix processors

enabling a 45% reduction in power consumption.